1. Field of the Invention
This invention relates to a method for fabricating an electrostatic-discharge (ESD) protection circuit using a field device, and more particularly to forming a field device with a low threshold voltage in an ESD protection circuit.
2. Description of Related Art
In the fabrication of an integrated circuit (IC), electrostatic-discharge (ESD) is one of the main factors causing IC damage. In order to solve ESD problems, an on-chip ESD protection circuit is fabricated directly on a bonding pad of, for example, a complementary metal-oxide semiconductor (CMOS) device. However, the ESD protection circuit is no longer effective protection because the threshold voltage of the IC device is reduced when the IC device is fabricated at a deep submicron or smaller dimension. The problems induced by ESD cause IC device failure. Hence, how the efficiency of an ESD protection circuit can be increased is an important issue for IC manufactures.
FIG. 1 is a circuit schematically illustrating a conventional ESD protection circuit, using a field effect transistor. In FIG. 1, an N-type field device is illustrated. Electrostatic charges from an input/output (I/O) port are discharged through a field device 10, such as a field device transistor, since the field device 10 is grounded to a ground voltage source Vss, in which the electrostatic charges also induce an over-stress voltage. The over-stress voltage passes a buffer gate 12 and into an internal circuit 14. The field device 10 therefore serves as an ESD element to protect the internal circuit 14 from the electrostatic charges induced by the I/O port, such as a bonding pad.
FIG. 2 is a cross-sectional view of a conventional field device transistor shown in FIG. 1. In FIG. 2, the field device transistor 10 of FIG. 1 is formed on a semiconductor substrate 20. The conventional field device transistor includes a field oxide layer 24 formed between a source region 22 and a drain region 23. For an N-type field device transistor, a P-type doped region 26 is conventionally formed below the field oxide layer 24. Then, the source region 22 is extended by an interconnect metal layer 27 to form a transistor source S, which is to be coupled to a ground voltage source Vss (FIG. 1). The interconnect metal layer 27 also extends the drain region 23 out to form a transistor drain D. Since the gate and the drain are directly coupled together, as shown in FIG. 1, the interconnect metal layer 27 also covers the field oxide layer 24 to effectively form a transistor gate G. The interconnect metal layer 27 is held by a dielectric layer 28.
For the conventional field device transistor 10 described above, when the over-stress voltage is inputted from the I/P port to the field device transistor 10, it activates the field device transistor 10 by a punch-through effect. Using the punch-through effect to activate the field device transistor 10 is faster than using the junction breakdown effect. The faster speed enables the field device transistor to prevent a gate oxide breakdown of a transistor in the internal circuit 14 at a low voltage from occurring due to the over-stress voltage.
However, in semiconductor fabrication, a P-type doped region is usually formed below a field oxide layer to increase isolation between device elements so that a P-type doped region 26 is also formed below the field oxide layer 24 in the field device transistor 10. This causes the field device transistor 10 to have a threshold voltage V.sub.T of about 12V-14V. The threshold voltage is the minimum voltage on the gate G necessary to activate the transistor 10. The threshold voltage V.sub.T of the field device transistor 10 thereby is greater than a breakdown voltage of a usual transistor. For example, the usual transistor, belonging to the internal circuit 14 and including its gate oxide layer with a thickness of about 50 .ANG., has a breakdown voltage of about 5V-6V. Hence, the field device transistor 10 with high V.sub.T of about 12V-14V is not suitable protection for the usual transistor with its gate oxide thickness of about 50 .ANG. in the internal circuit 14.